1. Field of the Invention
The present invention relates to a plasma display apparatus and a driving method thereof, and more particularly, to a plasma display apparatus which drives electrodes and a driving method thereof.
2. Description of the Background Art
Generally, in a plasma display panel, each cell is made by a barrier rib formed between a front substrate and a back substrate and main discharge gas such as Neon (Ne), Helium (He) or mixing gas (Ne+He) of Neon and Helium and inert gas containing small quantity of Xenon (Xe) are filled in an each cell. When the panel is discharged by a high frequency voltage, inert gas generates vacuum ultraviolet rays and allows a phosphor formed between the barrier ribs to emit light and thus an image is embodied. Since such a plasma display panel can be manufactured to be thin and have light weight, it is in the spotlight as a next generation display device.
FIG. 1 is a perspective view of general plasma display panel. As shown in FIG. 1, in the plasma display panel, a front substrate 100 that is a display surface in which an image is displayed and a back substrate 110 forming a back surface are coupled to each other with disposed in parallel apart by a predetermined distance.
The front substrate 100 is formed by a pair of a scan electrode 101 and a sustain electrode 102 for discharging to each other in one discharge cell and sustaining light emitting of a cell, that is, a scan electrode 101 and the sustain electrode 102 having a transparent electrode made of a transparent ITO material and a bus electrode made of a metal material. The scan electrode 101 and the sustain electrode 102 limits a discharge current and are covered with one or more dielectric layer 103 for isolating pairs of electrodes, and a protective layer 104 deposited with Magnesium Oxide (MgO) is formed on the upper surface of the dielectric layer 103 to facilitate a discharge condition.
The back substrate 110 is formed by disposing in parallel a stripe-type (or well type) barrier rib 111 for forming a plurality of discharge spaces, that is, discharge cells. Further, a plurality of address electrodes 112 generating vacuum ultraviolet rays by performing address discharge are disposed in parallel to the barrier rib 111. RGB phosphors 113 emitting visible rays for displaying an image when the address discharge is performed are coated on an upper side surface of the back substrate 110. White dielectric substance 114 for protecting the address electrode 112 and reflecting visible rays emitted from the phosphor 113 to the front substrate 100 is formed between the address electrode 112 and the phosphor 113.
A method of embodying an image gray level in such a plasma display panel will be described with reference to FIG. 2.
FIG. 2 is a diagram illustrating a method of embodying the image gray level of a conventional plasma display apparatus. As shown in the figure, in a method of expressing a image gray level of the conventional plasma display apparatus, one frame is divided into several subfields having the different light emitting number and each subfield is again divided into a reset period (RPD) for initializing all cells, the address period (APD) for selecting a cell to be discharged, and the sustain period (SPD) for embodying a gray level depending on the number of the discharge. For example, when an image is displayed in 256 gray levels, a frame period (16.67 ms) corresponding to 1/60 second is divided into 8 subfields (SF1 to SF8) and each of 8 subfields (SF1 to SF8) is again divided into the reset period, the address period, and the sustain period.
The reset period and the address period of each subfield are equal in each subfield. The address discharge for selecting a cell to be discharged is generated by the voltage difference between an address electrode and a transparent electrode that is a scan electrode. The sustain period is increased in a ratio of 2n (n=0, 1, 2, 3, 4, 5, 6, 7) in each subfield. In this way, since the sustain period is different in each subfield, by adjusting the sustain period of each subfield, that is, the sustain discharge number, the gray level of an image is expressed. Driving waveforms according to a driving method of the plasma display apparatus is shown in FIG. 3.
FIG. 3 is a diagram illustrating driving waveforms according to a driving method of the conventional plasma display apparatus. As shown in the figure, the plasma display apparatus is driven by dividing the period into the reset period for initializing all cells, the address period for selecting cells to discharge, the sustain period for sustaining the discharge of the selected cell, and an eraser period for erasing wall charges within the discharged cell.
At the reset period, a ramp-up waveform is simultaneously applied to all scan electrodes at a setup period. Weak dark discharge occurs in discharge cells of a full screen by the ramp-up waveform. Positive polarity wall charges are stacked on the address electrode and the sustain electrode and a negative polarity wall charges are stacked on the scan electrode, by the setup discharge.
At a setdown period, after a ramp-up waveform is supplied, because a ramp-down waveform falling from a positive polarity voltage lower than a peak voltage of the ramp-up waveform to a specific voltage level of a ground (GND) level voltage or less causes feeble eraser discharge within cells, wall charges excessively formed in the scan electrode are fully erased. Wall charges enough to stably cause the address discharge by the setdown discharge uniformly remain within cells.
At the address period, when a negative polarity scan signal is sequentially applied to the scan electrodes, a scan signal is simultaneously synchronized and thus a positive polarity data signal is applied to the address electrode. The address discharge is generated within the discharge cells to which the data signal is applied while the wall voltage generated at the reset period is added to the voltage difference of the scan signal and the data signal. Wall charges enough to cause the discharge are formed when the sustain voltage (Vs) is applied within cells selected by the address discharge. A positive polarity voltage (Vz) is supplied to the sustain electrode to prevent mis-discharge from generating between the sustain electrode and the scan electrode by decreasing the voltage difference from the scan electrode during the setdown period and the address period.
At the sustain period, sustain signals (Sus) are alternatively applied to the scan electrode and the sustain electrodes. A cell selected by the address discharge generates the sustain discharge, that is, display discharge between the scan electrode and the sustain electrode whenever each sustain signal is applied while a sustain signal is added to the wall voltage within the cell.
At the eraser period, after the sustain discharge is completed, a voltage of ramp-ers having small pulse width and voltage level is supplied to the sustain electrode to erase wall charges remaining within cells of an entire screen.
A conventional plasma display apparatus for generating and supplying the driving waveform will be described with reference to FIG. 4.
FIG. 4 is a circuit diagram of the conventional plasma display apparatus. As shown in the figure, the conventional plasma display apparatus includes a sustain voltage supply unit 40, a setup supply unit 41, a scan voltage supply unit 42, a driving signal output unit 43, a setdown supply unit 44, a negative polarity scan voltage supply unit 45, a seventh switch (Q7) connected between the setup supply unit 41 and the driving signal output unit 43, and a sixth switch (Q6) connected between the setup supply unit 41 and the sustain voltage supply unit 40.
The driving signal output unit 43 is connected in a push-pull type and is composed of a twelfth and a thirteenth switch (Q12, Q13) for inputting a voltage signal from the sustain voltage supply unit 40, the setup supply unit 41, the scan voltage supply unit 42, the setdown supply unit 44, and the negative polarity scan voltage supply unit 45. An output line between the twelfth and the thirteenth switch (Q12, Q13) is connected to the panel (Cp), preferably to one of scan electrode lines of the panel (Cp).
The sustain voltage supply unit 40 includes a energy supply and recovery capacitor (C1) for charging energy recovered from the panel (Cp), an inductor (L1) connected between the energy supply and recovery capacitor (C1) and a drive integrated circuit 43, and a first switch (Q1), a first diode (D1), a second switch (Q2), and a second diode (D2) connected in parallel between the inductor (L1) and the energy supply and recovery capacitor (C1). The sustain voltage supply unit 40 decreases excessive consumption power at the discharge during the setup period and the sustain period by supplying a voltage to the panel (Cp) using the recovered energy after recovering an energy from the panel (Cp).
The scan voltage supply unit 42 includes a third capacitor (C3) connected between a scan voltage source (Vsc) and a second node (n2) and an eighth switch (Q8) and a ninth switch (Q9) connected between the scan voltage source (Vsc) and the second node (n2). While the eighth switch (Q8) and the ninth switch (Q9) are switched by a control signal supplied from a timing controller during the address period, they supply a voltage of the scan voltage source (Vsc) to the drive integrated circuit 43. The third capacitor (C3) adds a voltage of the scan voltage source (Vsc) to a voltage applied to the second node (n2) and thus supplies the sum voltage to the eighth switch (Q8).
The setup supply unit 41 includes a third diode (D3) and a fifth switch (Q5) connected between the setup voltage source (Vst) and the first node (n1) and a second capacitor (C2) provided between the setup voltage source (Vst) and the sustain voltage supply unit 40. The third diode (D3) intercepts a backward current flowing from the second capacitor (C2) toward the setup voltage source (Vst). The second capacitor (C2) adds a voltage of the setup voltage source (Vst) to the sustain voltage (Vs) supplied from the sustain voltage supply unit 40 and thus supplies the sum voltage to the fifth switch (Q5). The fifth switch (Q5) is switched by responding to a control signal that is not shown during the reset period and thus supplies the setup voltage to the first node (n1).
The setdown supply unit 44 includes a tenth switch (Q10) connected between the second node (n2) and a negative polarity scan voltage (−Vy). The setdown supply unit 44 slowly falls a voltage supplied from the driving signal output unit 43 during the setdown period included in the reset period to a negative polarity scan voltage (−Vy) in a predetermined slope. Here, the negative polarity scan voltage (−Vy) is used as the setdown power source.
The negative polarity scan voltage supply unit 45 includes an eleventh switch (Q11) connected between the second node (n2) and the negative polarity scan voltage source (−Vy). The eleventh switch (Q11) is switched by responding to a control signal supplied from the timing controller which is not shown during the address period and thus supplies the negative polarity scan voltage (−Vy) to the driving signal output unit 43.
A process of generating a reset waveform of the reset period among driving waveforms shown in FIG. 3 in a conventional driving apparatus of the plasma display panel will be described with reference to FIG. 5.
FIG. 5 is a timing chart illustrating a switching operation for generating a ramp-up waveform at the reset period in the driving apparatus of the conventional plasma display panel. Here, it is supposed that a voltage (Vst) of a setup voltage source is charged in the second capacitor (C2).
First, during the setup period, the fifth switch (Q5) and the seventh switch (Q7) are turned-on and the sixth switch (Q6) and the tenth switch (Q10) are turned-off. At this time, the sustain voltage (Vs) is supplied from the sustain voltage supply unit 40. The sustain voltage (Vs) supplied from the sustain voltage supply unit 40 is supplied to the panel (Cp) via an inside diode of the sixth switch (Q6), the seventh switch (Q7), and the driving signal output unit 43. Therefore, a voltage of the panel (Cp) is rapidly raised to a voltage Vs.
On the other hand, the setup voltage (Vst) stored in the second capacitor (C2) is added to the voltage (Vs) of a sustain voltage source and thus the sum voltage is supplied to the fifth switch (Q5). While the fifth switch (Q5) adjusts a channel width by a first variable resistor (VR1) provided in the front terminal thereof, it supplies a voltage supplied from the second capacitor (C2) to the first node (n1) in a predetermined slope. A voltage applied to the first node (n1) in a predetermined slope is supplied to the panel (Cp) via the seventh switch (Q7) and the driving signal output unit 43. At this time, a ramp-up waveform is supplied to the panel (Cp).
After the ramp-up waveform is supplied to the panel (Cp), the fifth switch (Q5) is turned-off. When the fifth switch (Q5) is turned-off, only a voltage Vs supplied from the sustain voltage supply unit 40 is applied to the first node (n1), so that the voltage of panel (Cp) rapidly falls to a voltage Vs.
The setup supply unit 41 supplies the ramp-up waveform to the panel (Cp) during the reset period while repeating such a process.
There is a problem in that the conventional driving apparatus of the plasma display panel has the relatively expensive production cost. For example, the production cost is increased by using the sixth switch (Q6) having a high dielectric strength. That is, the sixth switch (Q6) performs a role of adding the sustain voltage Vs to the voltage Vst of the setup voltage source, but because it is positioned in a path to which the sustain pulse is supplied, it should be a high-capacity switching element having a high dielectric strength. Therefore, there is a problem in that the production cost is increased.
Further, a driving waveform in which the conventional plasma display panel generates may deteriorate a driving efficiency because a voltage of the reset period waveform is relatively low. That is, recently, a content of Xenon (Xe) within a discharge cell of the plasma display panel is increased, so that a discharge start voltage is increased. For example, on the assumption that the discharge generates in a voltage of 100V in previous case, if a content of Xenon (Xe) is increased, the discharge generates in a voltage of 150V. In this case, if a reset waveform of a conventional driving waveform is applied, reset discharge is unstable, so that a driving efficiency is decreased.